Apparatuses and methods for providing data from multiple memories

ABSTRACT

Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.

CROSS REFERENCED TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 13/219,417, filed on Aug. 26, 2011, and issued as U.S. Pat. No. 8,732,433 on May 20, 2014, which application and patent are incorporated herein by reference in their entirety and for any purpose.

TECHNICAL FIELD

Embodiments of the present invention relate to memories generally, and more particularly, in one or more embodiments, to a multi-memory system configured to provide read data using interleaved data outputs.

BACKGROUND OF THE INVENTION

As memory devices of all types have evolved, continuous improvements have been made to enhance performance in a variety of respects. Increases in memory bandwidth, capacity, and reliability have been implemented in an attempt to satisfy evolving demands, such as in applications requiring high quality video playback. To achieve better performance, manufacturers have utilized several approaches. For example, in some instances, the bit width of a data bus of a memory system may he increased to provide additional bandwidth to external devices. This is not a solution for all manufacturers, however, as many devices cannot feasibly be retooled to interface with a larger data bus bit-width.

Other issues often arise in design considerations as well. One such issue is the performance limitation of memory associated with memory access response times. Typically, accessing data in memory may require that an address of memory first be sensed, and data corresponding to that address provided to a data bus. Thus, if a memory receives too many read commands within a particular time period, each command cannot be fully executed before the next command is received, and an output of incorrect or corrupt data may result. A sense operation in particular may incur substantial delays, limiting the frequency at which read commands may be executed, and as a result, also the rate at which data can be provided. Because the amount of time required to complete memory accesses is based at least in part by physical characteristics of the memory itself, increasing response times to improve output may not always be possible.

In some cases, designs can be implemented to increase performance, but at a cost of functionality. For example, some memories may be configured to execute page reads at a higher rate than other memories, but may be limited in their ability to efficiently respond to more random requests of read data. In other instances, memory designs may allow for more efficient operation, but may also limit the number of memories that can simultaneously operate in a memory system.

Therefore, a need exists for a system and method to provide improved data output without increasing data bus bit-width, limiting functionality, or increasing the frequency of read commands provided to a memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an embodiment of an electronic system according to an embodiment of the invention.

FIG. 2 is a block diagram of an embodiment of a memory system that may be used in the system of FIG. 1 according to an embodiment of the invention.

FIG. 3 is a timing diagram for a method of operation of the memory system in FIG. 2 according to an embodiment of the invention.

FIG. 4A is a timing diagram for a method of operation of the memory system in FIG. 2 according to an embodiment of the invention.

FIG. 4B is a timing diagram for a method of operation of the memory system in FIG. 2 according to an embodiment of the invention.

FIG. 5 is a block diagram of an embodiment of a memory system used in the system of FIG. 1 according to an embodiment of the invention.

FIG. 6 is a timing diagram for a method of operation of the memory system in FIG. 5 according to an embodiment of the invention.

DETAILED DESCRIPTION

Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.

FIG. 1 illustrates an apparatus in the form of an electronic system 100 according to an embodiment of the invention. A memory system 110 is coupled to a memory access device, such as a memory controller 105, by a communication bus 150. The memory system 110 may comprise a plurality of memories which may be identical to each other. Communication bus 150 may couple memory controller 105 to memories of the memory system 110 and may comprise a data bus, control bus, and/or an address bus. It will be appreciated by those having ordinary skill in the art, however, that any number of busses may be used to couple memory controller 105 and the memory system 110. Memory controller 105 may be configured to provide control (e.g., chip enable and/or output enable signals) and address signals to memory system 110 over communication bus 150, and may also provide and/or receive data signals to/from memory system 110 over communication bus 150.

FIG. 2 illustrates an apparatus in the form of a memory system 200 according to an embodiment of the invention. The memory system 200 may be used for the memory system 110 of FIG. 1. The memory system 200 includes memories 202, 204. Memories 202, 204 may be coupled to a chip enable bus 209 and an address bus 210. According to one example embodiment, a bus can comprise one or more communication paths (e.g., conductive lines). A chip enable signal CE# is provided to the memories 202, 204 on the chip enable bus 209 and address signals ADD are provided to the memories 202, 204 on the address bus 210. Addresses of memory locations of the memories 202, 204 are represented by the ADD signals. Memories 202, 204 may also be coupled to a data bus 211 and configured to receive output enable signals OE0# and OE1#, respectively. The data bus 211 has a bus width (e.g., the number of communication paths) that is typically defined in a number of bits of the data provided on the data bus 211. The bus width of the data bus 211 may be the same width as the outputs of each of the memories 202, 204. That is, the data bus 211 may be only wide enough to provide/receive data to/from one of the memories 202, 204 at a time. In some embodiments, the bus width is 16-bits wide. The data bus 211, however, may be other widths as well. Although the memory system 200 includes memories 202, 204, other embodiments of the memory system 200 may use a greater or lesser number of memories. The memory system 200 is configured to provide approximately the same amount of data per memory command as a memory system configured to provide data of 2N bits wide although the data bus 211 of the memory system 200 has a bus width of N bits.

In at least one embodiment, address and control signals provided to memories 202, may be provided by a memory controller, for example, memory controller 105 system 100 as shown in FIG. 1. In other embodiments, signals may be received from any memory access device (e.g., control logic) as is well known in the art. It will be appreciated by those having ordinary skill in the art that other implementations may also be used without departing from the scope of the present invention.

FIG. 3 illustrates a timing diagram of various signals during operation of a memory system according to an embodiment of the invention, for example, the memory system 200 illustrated in FIG. 2. The timing diagram of FIG. 3 will be described with reference to the memory system 200. In operation, memories 202, 204 may receive the CE# signal via chip enable bus 209. This may enable memories 202, 204 to receive or provide (e.g., transmit) data as part of the execution of memory commands, such as read commands. Moreover, the ADD signals may be received via address bus 210, such as to identify a particular group (e.g., a row or page of a row) of memory locations in each respective memory. In some embodiments, memories 202, 204 may receive the same address via a shared address bus 210. Address bus 210 may have a bit-width of, for example, 16, 32, or 64-bits, or may have any other bit-width. In at least one embodiment, addresses on address bus 210 may comprise a plurality of group (e.g., row) address bits (e.g., bits 26:4 on the address bus) and a plurality of page address bits (e.g., bits 3:0 on the address bus). For example, an address may comprise 28 row address bits and 4 page address bits. It will be appreciated by those having ordinary skill in the art, however, that addresses may have any number of bits and/or ratio of group (e.g., row) address bits to page address bits without departing from the scope of the present invention. As used hereinafter, an “address” can refer to a group address and/or a page address.

When an address represented by the ADD signals is provided, memories 202, 204 may automatically detect a signal transition of one or more of the ADD signals provided on the address bus 210. Responsive to detecting a signal transition, the memories 202, 204 may begin a memory access operation, for example, a read operation, in anticipation of accessing the memory location corresponding to the address. A typical memory access operation includes a sense operation where data for a group of memory locations corresponding to the address is sensed and then followed, in the case of a read operation, by a data output operation where data from the sensed group of locations is provided to a data bus by the memories 202, 204. Of the total time for a memory access operation, the sense operation may take the majority of the time, with the data output operation taking the remaining time. For example, in an example of a memory access operation taking 100 ns, the sense operation may take approximately 75 ns and the data output operation may take approximately 25 ns. Those ordinarily skilled in the art will appreciate that the specific times have been provided by way of example and that they are not intended to limit the scope of the present invention.

The sense operation may comprise memories 202, 204 accessing the group of memory locations corresponding to the address and coupling the data stored by at least a subset (e.g., a page) of the group of memory locations to a plurality of sense amplifiers (not shown). As will be described in more detail below, after a particular time has passed such that memories 202, 204 have completed sensing the data output operation may be performed. The output enable signals OE0# and OE1#, provided to memories 202, 204, respectively, may be activated (i.e., active low) to individually enable the outputs of each memory allowing each to selectively provide data onto the data bus. For example, the OE0# signal may be activated to enable the memory 202 to provide data onto the data bus 211, followed by activating the OE1# signal to enable the memory 204 to provide data onto the data bus 211. With respect to FIG. 3, Tacc represents the time for a memory to provide data after the memory is enabled, for example, in response to a signal transition of an ADD signal. That is, after a transition of the ADD signals provided on the address bus 210 is detected (representing a new address) and Tacc has elapsed the data corresponding to the address will be provided.

With reference to FIG. 3, at time T0, a first address represented by the ADD signals may be provided to memories 202, 204 via address bus 210. The memories 202, 204 may begin sensing data in response to detecting a transition of the ADD signals. As previously described, after a particular period of time has elapsed during which the memories 202, 204 have completed sensing, represented in FIG. 3 as time T1, the output enable signal OE0# may be made active to allow memory 202 to provide sensed data corresponding to the first address to data bus 211. At time T2, the data output operation (following the sense operation) has completed and the sensed data is ready to be provided. Further at time T2, memory 202 provides data to data bus 211.

A second address may also be provided on address bus 210 to memories 202, 204 at time T2. The memories 202, 204 may detect a signal transition of the ADD signals for the second address and begin the sense operation for the data corresponding to the second address.

After the data is provided by the memory 202 to the data bus 211 resulting from a data output operation, the output enable signal OE0# may be deactivated to disable the output of memory 202, as shown in FIG. 3 at time T3. At time T4, the output enable signal OE1# may be activated to allow memory 204 to provide data corresponding to the first address to data bus 211. At time T5, memory 204 may provide data corresponding to the first address onto data bus 211. Note that the memory 204 provides data before the sense operation for the second address is completed. The OE1# signal may be toggled, for example, at time T6, to disable the output of memory 204.

Data corresponding to the second address may be provided to the data bus 211 in substantially the same manner as for the data corresponding to the first address. For example, at time T7 the OE0# signal is activated to enable the output of the memory 202. The data corresponding to the second address is provided at time T8 by the memory 202 to the data bus 211. The OE0# signal is deactivated at time T9 and the OE0# signal is activated at time T10. As a result, the memory 204 provides the data corresponding to the second address at time T11. The OE1# signal is deactivated at time T12 to disable the output of the memory 204.

In at least one embodiment, the amount of time for the memories 202, 204 to provide the same amount of data in an interleaved manner to a data bus 211 having a bus width of N (e.g., 32-bits of data, 16-bits provided by each memory in an interleaved manner to a 16-bit bus) is no more than the amount of time for memories 202, 204 to simultaneously provide the data, using a data bus having a bus width of 2N (e.g., 32 bits,16-bits provided by each memory simultaneously to a 32-bit bus). The interleaved operation takes advantage of the time for the sense operation to complete in that at least a portion of the data for a previous address may be provided during a sense operation for a subsequent address. The data corresponding to the previous address, however, should be provided by the memories 202, 204 before the sensing operation for the subsequent address completes. If the sensing of the subsequent address completes before data of the previous address is provided by the memories 202, 204, data provided to data bus 211 may be corrupted.

In some embodiments, a greater number of memories may be used, provided the time required to sequentially provide data from all memories is less than the time required for all memories to sense data in response to a subsequent address. For example, in one embodiment, the sense operation requires 75 ns to complete, while the data output operation requires 10 ns per memory. Under these circumstances, data from up to 7 memories of a memory system may be sequentially provided.

FIGS. 4A and 4B illustrate timing diagrams of various signals during operation of a memory system according to an embodiment of the invention. For example, the operation illustrated by FIGS. 4A and 4B may be used with the memory system 200 illustrated in FIG. 2. The timing diagrams of FIGS. 4A and 4B will be described with reference to the memory system 200. FIG. 4A shows a timing diagram for a method of operation of the memory system 200 in FIG. 2 utilizing an interleaved read from memories 202, 204. At time T0, ADD signals representing a first address are provided to memories 202, 204 via address bus 210. In response, the memories 202, 204 may begin the sense operations to begin simultaneously sensing data. After the sense operations have completed the data output operation is performed to provide the data corresponding to the first address. The output enable signal OE0# may be activated (shown in FIG. 4A at time T1) to enable the memory 202 to provide the data corresponding to the first address. At time T2, the memory 202 provides data to the data bus 211 and at time T3, the OE0# signal is deactivated to disable the output of the memory 202.

As previously described, addresses provided on address bus 210 may contain a plurality of page address bits that may be used to identify as particular subset of memory locations in a group of memory locations (i.e., page) of memory. For example, when a sense operation is performed, at least a subset of memory locations in a row of memory is sensed, and particular data in the sensed portion of the row may be identified by page bits of the address. Because much of the time of a sense operation involves opening a row in memory, accessing different data in a row already opened may not require a full sense operation.

At time T2, second page address bits identifying another particular subset of memory locations in the open row of memory from the first address is provided to memories 202, 204, as represented by the transition in page bits of the ADD signals. The memories 202, 204 may detect the transition on address bus 210 at time T2 and begin providing the data corresponding to the second address. At time T3, the OE0# signal is deactivated to disable the output of the memory 202, and at time T4, the output enable signal OE1# may be activated to allow memory 204 to provide data corresponding to the first address. Data is provided by the memory 204 to the data bus 211 at time T5 and at time T6, the OE1# signal is deactivated to disable the output of the memory 204.

As discussed above, because consecutive addresses provided to the memories 202, 204 identify data in the open row of memory (i.e., data already sensed), it may not be necessary to delay for a sense operation before providing data onto the data bus 211 corresponding to the subsequent address in the same open row. Thus, data corresponding to the second address can be provided sooner than in the case for data corresponding to the first address, and the data may be provided by the memories 202, 204 applying substantially the same sequence of signals as for providing the data corresponding to the first address. For example, at a time T7, output enable signal OE0# may be activated to allow memory 202 to provide (e.g., output) data corresponding to the second address. At time T8, data of the second address is provided by the memory 202 to the data bus 211. The OE0# signal is deactivated at time T9 to disable the output of memory 202 and the OE1# signal is activated at time T10 to enable the output of the memory 204. Data corresponding to the second address is provided by the memory 204 to the data bus 211 at time T11 and the output of the memory 204 is disabled by deactivating the OE1# signal at time T12. Also at time T8, a third address is provided to the memories 202, 204 and the process for accessing additional data from the open row of memory begins, as previously discussed with reference to the data corresponding to the second address.

As illustrated in the example of FIG. 4A, the memories 202, 204 are operated to provided data in an interleaved manner. At least a portion of the data corresponding to a memory address is provided by the memories 202, 204 during a sensing operation performed for a subsequent address provided to the memories 202, 204. In another embodiment, a greater number of memories may be used by coordinating the operation of each of the memories through the timing of the various signals so that the memories may provide data in an interleaved manner.

FIG. 4B illustrates a timing diagram for a method of operation of the memory system 200 in FIG. 2 utilizing an interleaved read from memories 202, 204. At time T0, ADD signals representing a first address are provided to memories 202, 204 via address bus 210. In response, the memories 202, 204 begin a sense operation. After the sense operation has completed, the output enable signal OE0# may be activated, as shown at time T1 to enable the output of memory 202 so that data may be provided to data bus 211. At time T2, the memory 202 provides the data corresponding to the first address to the data bus 211.

In contrast to the operation described with reference to FIG. 4A, at time T2, a second address is provided to the memories 202, 204 on address bus 210 to request a second data from the open row of memory to be provided, by the same memory 202. As illustrated in FIG. 4B, a plurality of new addresses may be consecutively provided to memories 202, 204 over address bus 210, causing the memory 202 to provide the data from the open row corresponding to the respective address. The addresses provided to the memories 202, 204 may be related by incrementing page bits, for example, or may be random within the open row of memory. The data corresponding to each of the addresses may be sequentially provided to the data bus 211 by the memory 202, illustrated in FIG. 4B at times T2, T3, T4, and T5. The OE0# signal is deactivated at time T6 to disable the output of the memory 202.

At a time T5, a new first address is provided to memories 202, 204. At time T7, the output of memory 204 may be enabled by activating the OE1# signal such that the memory 204 will provide data to the data bus 211. As a result of disabling the output of memory 202 at time T6 and enabling the output of memory 204 at time T7, data corresponding to the new addresses are provided from memory 204 instead of memory 202. The data corresponding to the new addresses are provided by the memory 204, as illustrated in FIG. 4B at times T8, T9, T10, and T11. As described with reference to the timing diagram of FIG. 4B, data from an open row of memory may be first sequentially provided by one of the memories (e.g., memory 202) and then sequentially provided by the other one of the memories (e.g., 204) from the same or another row of open memory.

FIG. 5 illustrates a memory system 500 according to an embodiment of the Invention. The memory system 500 includes memories 502, 504. Memories 502, 504 may be coupled to a chip enable bus 509 and an address bus 510. A chip enable signal CE# is provided to the memories 502, 504 on the chip enable bus 509 and address signals ADD are provided to the memories 502, 504 on the address bus 210. Addresses of memory locations of the memories 502, 504 are represented by the ADD signals. Memories 502, 504 may also be coupled to a data bus 511 and configured to receive output enable signals OE0# and OE1#, respectively. The data bus 511 has a bus width that is typically defined in the number of bits of the data provided on the data bus 511. In some embodiments, the bus width is 16-bits wide. The data bus 211, however, may be other widths as well. Memories 502, 504 may further be configured to receive address valid signals ADV0# and ADV1#, and although the memory system 500 includes memories 502, 504, other embodiments of the memory device may use a greater number of memories. The memory system 500 is configured to provide approximately the same amount of data per memory command as a memory system configured to provide data of 2N bits wide although the data bus 211 of the memory system 500 has a bus width of N bits.

In at least one embodiment, address and control signals provided to memories 502, 504 may be provided by a memory controller 105 of system 100 as shown in FIG. 1. In other embodiments, signals may be received from any other memory access device, as is well known in the art. It will be appreciated by those having ordinary skill in the art that other implementations may also be used without departing from the scope of the present invention.

FIG. 6 illustrates a timing diagram of various signals during operation of a memory system according to an embodiment of the invention, for example, the memory system 500 illustrated in FIG. 5. The timing diagram of FIG. 6 will be described with reference to the memory system 500. In operation, memories 502, 504 may receive the CE# signal via chip enable bus 509. This may enable memories 502, 504 to receive or provide data as part of the execution of memory commands, such as read commands. Moreover, the ADD signals may be received via address bus 510 to identify a particular row of data in each respective memory. In some embodiments, memories 502, 504 may receive the same address via address bus 510. Address bus 510 may have a bit-width of, for example, 16, 32, or 64-bits, or may have any other bit-width. In at least one embodiment, addresses on address bus 510 may comprise a plurality of row address bits and a plurality of page address bits. For example, an address may comprise 22 row address bits and 4 page address bits. It will be appreciated by those having ordinary skill in the art, however, that addresses may have any number of bits and/or ratio of row address bits to page address bits without departing from the scope of the present invention.

In contrast to the operation of the memory system 200, memories 502, 504 may not automatically detect a transition of one or more of the ADD signals provided on address bus 510 and begin a respective memory access (e.g., sense) operation responsive to detecting the transition. Instead, activating the address valid signal ADV0# or the address valid signal ADV1# signals may trigger performance of the access operation on the memories 502, 504, respectively. The memory provided an address may begin a memory access operation, for example, a read operation, in anticipation of accessing the memory location corresponding to the address. Typical memory access operations includes a sense operation and in the case for a read operation, a data output operation. As discussed above, when a sense operation is performed, a particular subset of memory locations in a group of memory locations is sensed, and particular data corresponding to the memory locations in the row may be identified by page bits. Because a portion of a sense operation involves opening at least a portion of a row in memory, accessing different data in a row already opened may not require a full sense operation. Thus, a plurality of addresses may be consecutively provided to a memory, causing the memory to provide the data from the open row corresponding to the respective address.

As will be described in more detail below, after a particular period of time has passed such that a memory provided with an address has completed sensing, the data output operation may be performed, and either the OE0# signal or the OE1# signal may be activated to enable memory 502 or memory 504, respectively, to provide data onto the data bus 511.

FIG. 6 illustrates a timing diagram for a method of operation of the memory system 500 in FIG. 5 utilizing mimicked burst mode reads from memories 502, 504. At time T0, ADD signals representing a first address are provided to memories 502, 504 via address bus 510. The ADV0# may be activated to cause memory 502 to trigger a sense operation to be performed for the first address on address bus 510. After the sense operation has completed, at time T1, a second address is provided to memory 502 on address bus 510 to request a second data from the open row of memory to be provided by memory 502. Additionally, the output enable signal OE0# may be activated to enable the output of memory 502 so that data may be provided to data bus 511. At time T2, the memory 502 provides the data corresponding to the first address to the data bus 511. As illustrated in FIG. 6, a plurality of new addresses may be consecutively provided to memory 502 over address bus 510, causing the memory 502 to provide the data from the open row identified by the respective address. The addresses provided to memory 502 may be related by incrementing, or may be random, within the open row of memory. Data corresponding to each of the addresses may be sequentially provided to the data bus 511 by the memory 502, as illustrated in FIG. 6 at times T2, T3, T4, and T5. The OE0# signal is deactivated at time T5 to disable the output of memory 502.

A sense operation may be performed for a new initial address provided to memory 504 via address bus 510 at time T2 responsive to address valid signal ADV1# being activated. At time T5, the 0E1# signal may be activated to enable the output of memory 504. As a result of disabling the output of memory 502 and enabling the output of memory 504 at time T5, memory 504 provides data to the data bus 511 instead of memory 502. Data corresponding to the new addresses are provided by the memory 502 as illustrated in FIG. 6 at times T6, T7, T8, and T9.

Data corresponding to the third address from time T6 may be provided to the data bus 211 in substantially the same manner as for the data corresponding to the first address. For example, at time T9, the OE0# signal is activated and the OE1# signal is deactivated. Data for the third address is provided by memory 502 at time T10 to data bus 511.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims. 

What is claimed is:
 1. A method, comprising: receiving a common chip enable signal at both a first memory and a second memory; receiving a first address at the first memory and the second memory; performing a sense operation for the first address in the first memory and the second memory; receiving a second address at the first memory and the second memory; outputting data corresponding to the first address and the second address from the first memory; receiving a third address at the first memory and the second memory; and outputting data corresponding to the third address from the second memory after outputting data from the first memory.
 2. The method of claim 1, wherein the third address is the same as the first address.
 3. The method of claim 1, wherein the first address and the second address are from a same row of memory.
 4. The method of claim 3, wherein the first address and the second address random within the same row of memory.
 5. The method of claim 1, wherein the first address and the second address are related by incrementing page bits.
 6. The method of claims 1, further comprising: providing the common chip enable signal to the first memory and the second memory; providing the first address to the first memory and the second memory; providing the second address to the first memory and the second memory; receiving the data corresponding to the first address and the second address from the first memory; and receiving the data corresponding to the first address and the second address from second memory after receiving the data from the first memory.
 7. The method of claim 1, wherein the outputting data corresponding to the first address and the second address from the first memory is responsive to receiving a corresponding output enable signal.
 8. The method of claim 1, wherein the data corresponding to the first and second addresses are output from the first and second memories in an interleaved manner.
 9. A method, comprising: receiving a common chip enable signal at both a first memory and a second memory; receiving a first address at the first memory and the second memory; performing a sense operation for the first address in the first memory: receiving a plurality of addresses at the first memory; outputting data corresponding to the first address from the first memory; and outputting data corresponding to the plurality of addresses from the first memory receiving a new address at the second memory; performing a sense operation for the new address in the second memory; and outputting data corresponding to the new address from the second memory after outputting data from the first memory.
 10. The method of claim 9, wherein the new address is the same as the first address.
 11. The method of claim 9, wherein the performing the sense operation is responsive to receiving a corresponding address valid signal.
 12. The method of claim 9, wherein the outputting data is responsive to receiving a corresponding output enable signal.
 13. The method of claim 9, wherein the data corresponding to the plurality of addresses is output sequentially.
 14. The method of claim 9 further comprising receiving a third address at the second memory.
 15. The method of claim 14, wherein the third address corresponds to a different row in the second memory than the first address.
 16. The method of claim 9, wherein the data corresponding to the plurality of addresses is output in a mimicked burst mode manner.
 17. An apparatus, comprising: a plurality of memories configured to receive a common enable signal and to output data responsive, at least in part, to a first address received at the plurality of memories; wherein a memory of the plurality of memories is further configured to output at least a portion of the data corresponding to the first address during a sense operation for a second address received by the plurality of memories after the first address and further configured to output data corresponding to the second address after the sense operation is completed.
 18. The apparatus of claim 17, wherein the memory of the plurality of memories is configured to output data responsive to receiving a respective output enable signal.
 19. The apparatus of claim 17, wherein the memory of the plurality of memories is configured to perform the sense operation responsive to receiving a corresponding address valid signal.
 20. The apparatus of claim 17, wherein each of the plurality of memories is configured to receive a respective output enable signal.
 21. The apparatus of claim 17, wherein each of the plurality of memories is configured to receive a respective address valid signal.
 22. An apparatus, comprising: a memory controller; a communication bus coupled to the memory controller; and a memory system coupled to the memory controller by the communication bus, the memory system including: a plurality of memories configured to receive a common enable signal and to output data responsive, at least in part, to a first address received at the plurality of memories; wherein a memory of the plurality of memories is further configured to output at least a portion of the data corresponding to the first address during a sense operation for a second address received by the plurality of memories after the first address, and further configured to output data corresponding to the second address after the sense operation is completed; wherein the memory controller is configured to provide the common enable signal, the first address, and the second address to the memory system.
 23. The apparatus of claim 22, wherein the memory controller is further configured to receive the data output by the plurality of memories.
 24. The apparatus of claim 22, wherein the memory controller is further configured to provide an address valid signal to the memory of the plurality of memories.
 25. The apparatus of claim 22, wherein the memory controller is further configured to provide an output enable signal to a memory of the plurality of memories. 